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IEEE International High-Level Design, Validation and Test Workshop
(HLDVT 2010)

June 10-12, 2010
Anaheim, California, USA

http://www.hldvt.com/10


CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

HLDVT 2010 is the fifteenth in a series of annual workshops designed to bring together a community of researchers in the areas of design, validation, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum for researchers and practitioners to discuss the practical issues associated with simulation and validation of extremely large designs. 

The topics of interest include (but not limited to):

Simulation-Based Validation
Formal Verification
Design Abstraction & Behavioral Modeling
Error Trace Interpretation and Debugging
Hybrid SAT/BDD/ATPG Methods
On-Chip and Core-Based Testing
Test Generation for Defects, Design Errors, and Delay
Design/Synthesis for Test
Hardware/Software and Mixed-signal System Co-Validation
Emulation and Prototyping
Post-silicon Validation and Debug

Submissions

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The Program Committee invites authors to submit papers not to exceed 8 pages (IEEE two-column conference format with 10pt minimum font size) describing original and unpublished work. Panels and special session proposals are also invited. All submissions must be made electronically in PDF format using the paper submission webpage: http://www.hldvt.com/submissions. Please ensure that all the required contact details are entered during online submission.

Submission deadline: March 7, 2010
Acceptance Notification: April 6, 2010
Final manuscript: April 19, 2010

Paper Publication and Presenter Registration: The submission of a paper or panel proposal will be considered as evidence that upon acceptance, the author(s) will present their paper. For the papers to appear in the program and proceedings, required is at least one full workshop registration by an author before the submission of camera-ready version. IEEE reserves the right to exclude a paper from distribution (e.g., removal from IEEE Xplore) if the paper is not presented at the workshop. 

Key Dates

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Submission deadline: March 7, 2010
Notification of acceptance: April 6, 2010
Final copy deadline: April 19, 2010

Additional Information
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Questions regarding paper submissions and the program may be addressed to the program chair: Zeljko Zilic, programchair@hldvt.com.

Other questions may be addressed to the general chair: Prabhat Mishra, generalchair@hldvt.com.

Additional pertinent information will be made available at http://www.hldvt.com/10/.

Committees
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Organizing Committee

General Chair
Prabhat Mishra, Univ. of Florida

Program Chair
Zeljko Zilic, McGill University

Past Chair
Priyank Kalla, Univ. of Utah

Finance Chair
Hao Zheng, Univ. of South Florida

Publications Chair
Miroslav Velev, Aries Design Automation

Web Publicity Chair
Ismet Bayraktaroglu, Sun

Publicity Chair
Shireesh Verma, Conexant

Local Arrangements Chair
Ian Harris, UC Irvine

Industry Liaison
Shankar Hemmady, Synopsys

Panel/Special Session Chair
Sandeep Shukla, Virginia Tech


Program Committee

Samar Abdi, Concordia Univ.
Valeria Bertacco, Univ. of Michigan
Marc Boul´e, ´ Ecole de Tech. Sup´erieure
Ed Cerny, Synopsys
Pankaj Chauhan, Calypto
Tim Cheng, UC Santa Barbara
Franco Fummi, Univ. di Verona
John Hayes, Univ. of Michigan
Michael Hsiao, Virginia Tech
Alan Hu, Univ. British Columbia
Nicola Nicolici, McMaster Univ.
Priyadarsan Patra, Intel
Laurence Pierre, Univ. Grenoble
Wolfgang Rosenstiel, T¨ubingen Univ.
Pablo Sanchez, Univ. of Cantabria
Torsten Schober, IBM Germany
Li-C. Wang, UC Santa Barbara
Jin Yang, Intel
Avi Ziv, IBM

Steering Committee

Bernard Courtois, CMP-TIMA
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Blue Pearl Software

For more information, visit us on the web at: http://www.hldvt.com/10

The IEEE International High-Level Design, Validation and Test Workshop (HLDVT2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel. +1-514-398-6029
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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